A circuit array includes cells that are arranged in rows and columns, including, for example, row metal lines each coupled to a row of cells, and column metal lines each coupled to a column of cells. Accessing a cell involves enabling the cell through one of the row metal lines and the column metal lines, and passing data through the other of the row metal lines and column metal lines.
For example, for a static random access memory (SRAM) macro, each cell in the SRAM macro includes a storage device, a first access device, and a second access device. The storage device is configured with a storage node and a complementary storage node. The first access device is coupled between the storage node and a bit line and is controlled by a signal at a word line. The second access device is coupled between the complementary storage node and a complementary bit line and is controlled by the signal at the word line. The word line includes a metal line running along a row of cells. The bit line and complementary bit line include corresponding metal lines running along a column of cells. When a cell in the SRAM macro is accessed, a signal on the word line enables the row of cells for access. In this way, the first access device and second access device of the cell are turned on such that the corresponding bit line and the complementary bit line are coupled to the corresponding storage node and the complementary storage node. Further, data to be written or data read is passed along the bit line and the complementary bit line of the selected column of cells to or from the corresponding storage node and complementary storage node in the cell enabled for access.